--- title: "작은 구멍의 숨겨진 함정 – 기생 용량을 통해 PCB의 세 가지 물리적 메커니즘과 엔지니어링 솔루션 돌파" id: "16331" type: "우편" slug: "pcb-via-parasitic-capacitance-optimization" published_at: "2026-06-01T09:50:35+00:00" modified_at: "2026-06-01T09:53:46+00:00" url: "https://www.ugpcb.com/news/pcb-tech/pcb-via-parasitic-capacitance-optimization/" markdown_url: "https://www.ugpcb.com/news/pcb-tech/pcb-via-parasitic-capacitance-optimization.md" excerpt: "Imagine a high-speed PCB as a busy data city. The vias that carry signals between layers are like underground tunnels. According to the industry-standard approximation from IPC-2251, a typical through-hole via has a parasitic capacitance between 0.3 pF and 0.8..." taxonomy_category: - "PCB 기술" taxonomy_post_tag: - "백 드릴링" - "고속 PCB 설계" - "IPC 표준" - "low Dk material" - "PCB via parasitic capacitance" - "신호 무결성" - "via stub" --- Imagine a **[고속 PCB](https://www.ugpcb.com/product-category/pcb/high-speed-pcb/)** as a busy data city. The vias that carry signals between layers are like underground tunnels. According to the industry-standard approximation from IPC-2251, a typical through-hole via has a parasitic capacitance between 0.3 pF and 0.8 pF. When signal frequencies exceed 10 Gbps, this small number can cause reflections and delays. It can turn a perfectly designed data link into a bit error storm. This article analyzes the causes and optimization paths of via parasitic capacitance from three physical dimensions: 회로, field, and material. ## 1. The Capacitance Attenuation Layer – Controlling Geometric Dimensions to Reduce Electric Field Leakage The physical origin of via parasitic capacitance lies in the coupling between the via pad and the reference ground layer. From an electromagnetic field perspective, the pad and ground plane form a parallel-plate capacitor. To reduce via parasitic capacitance, the most direct path is to shrink the effective plate area. Industry practice follows minimum annular ring requirements. For IPC-6012 Class 3 높은 신뢰성, the outer layer minimum is 2 밀, while the inner layer can be reduced to 1 밀. This minimization strategy reduces the pad diameter and effectively compresses the coupling area with the ground plane. Increasing the hole-to-pad diameter difference provides another path to reduce capacitance. You must follow the formula: **Pad Diameter = Drill Diameter + 2 × Annular Ring** Drilling typically accounts for 30%–40% of **[PCB 제작](https://www.ugpcb.com/capacity/pcb-fabrication/)** 비용. 그러므로, via dimension adjustments require close coordination with economic constraints. For antipad treatment, removing copper around the pad on specific layers increases the spatial distance between conductors. 하지만, excessive clearance may cause crosstalk on adjacent traces and discontinuity in the reference plane. ## 2. The Dielectric Parameter Layer – The “Signal Slowdown Zone” in Material Selection Standard [FR-4 소재](https://www.ugpcb.com/why-us/pcb-material-list/s1000-2m-material/) has a relative dielectric constant Dk ≈ 4.2–4.8 at 1 GHz. ~에 10 GHz, the Dk value may drop by 5%–10%. Low Dk materials (Dk ≤ 3.5) effectively reduce via parasitic capacitance because capacitance is directly proportional to the dielectric constant. 하지만, these materials cost more and require harder processing. For ordinary low-speed circuits, you do not need to adopt this solution. IPC-4101 defines the technical boundaries for material selection. High-frequency designs must refer to the relevant Slash Sheet specifications in this standard. ## 3. The Electromagnetic Boundary Layer – Letting Signals Pass with Precision Controlling via stub length is a critical method for breaking through high-speed bottlenecks. ### **Engineering Threshold for Back Drilling** For 10 Gbps or higher SerDes channels, a stub length exceeding 10 밀 (~에 대한 0.254 mm) can cause observable insertion loss notches. Commercial back drilling processes can reliably control stub length between 4 mil and 8 밀 (0.1 mm to 0.2 mm). A via stub acts as an open-circuited transmission line stub. When the stub length equals one-quarter of the dielectric guided wavelength, it excites a high-Q series resonance. The return loss S11 can locally deteriorate beyond –8 dB. ### **Quantitative Judgment of Reflection Coefficient** The reflection coefficient formula is: **Γ = (Z₂ − Z₁) / (Z₂ + Z₁)** 어디: - Z₁ = line impedance before the reflection point - Z₂ = line impedance after the reflection point In an ideal case, Γ → 0 means full absorption with no reflection. Γ → ±1 means total reflection. When a via introduces additional parasitic parameters, Γ deviates from zero. Design must keep this deviation within an acceptable range through impedance control. ### **Via Barrel Wall Design Principles** At the microstructural level, via inner diameter, 종횡비 (보드 두께 / 구멍 직경), and copper plating thickness directly determine via mechanical reliability. Standard hole wall copper thickness ranges from 2.5 mil to 3.0 밀. The mechanical drilling limit for hole diameter is 6 밀 (0.15 mm). Laser drilling can reach 4 밀 (0.1 mm). When the aspect ratio exceeds 8:1, the plating solution cannot fully penetrate the hole center, and voids or cracks rise sharply. ### **Cost Trade-off for Blind and Buried Vias** Blind and buried vias can reduce parasitic capacitance to 1/3 또는 1/5 of a through-hole via. 하지만, their fabrication cost per square inch is about 1.3 에게 2.0 times higher than that of through-hole boards. Industry data shows that drilling accounts for 30%–40% of total PCB fabrication cost. Blind vias significantly increase this percentage due to their process complexity. Recommend using blind/buried vias only in these scenarios: system data rate ≥56 Gbps PAM4, **[HDI](https://www.ugpcb.com/product-category/pcb/hdi/)** any-layer interconnect for high routing density, or small packaging areas that cannot accommodate through-holes. ## Summary of Optimization Measures The table below summarizes all solutions and their cost impact based on the source material. | Optimization Category | Specific Measure | Cost Impact | | --- | --- | --- | | Via dimension design | Reduce pad diameter; increase hole-to-pad diameter difference | Minor – but watch mechanical strength and reliability | | Dielectric and isolation design | Increase dielectric distance; remove antipad; use low Dk material | Medium to High – low Dk material costs more | | Via placement design | Keep away from ground plane edges; control spacing to adjacent conductors | Minor – but requires safe clearance | | Via structure selection | Back drilling to remove stub; use blind/buried vias; reduce layer transition count | Medium to High – blind/buried vias cost 1.3–2.0x of through-holes | ## Get Professional Support for Your High-Frequency Via Optimization When your design team faces tough via optimization challenges for high-frequency signals, you need an experienced **[PCBA 공급업체](https://www.ugpcb.com/why-us/)**. We offer precise impedance simulation quotes and high-yield back drilling samples. Our fabrication capabilities meet IPC-6012 Class 3 high reliability standards and include mature HDI via structures. Click the button to request your custom design and manufacturing support. ## 참고자료 [1] IPC-2251, Design Guide for the Packaging of High Speed Electronic Circuits, IPC, 2003. [2] IPC-4101E/21, Specification for Base Materials for Rigid and Multilayer Printed Boards, IPC. [3] IPC-6012D, 경질 인쇄 기판의 자격 및 성능 사양, IPC. [4] IPC-D-317A4, Design Standard for Printed Board Assemblies, IPC. [5] IPC-TM-650, Test Methods Manual, IPC. **태그:**[백 드릴링](https://www.ugpcb.com/tag/back-drilling/) [고속 PCB 설계](https://www.ugpcb.com/tag/high-speed-pcb-design/) [IPC 표준](https://www.ugpcb.com/tag/ipc-standards/) [low Dk material](https://www.ugpcb.com/tag/low-dk-material/) [PCB via parasitic capacitance](https://www.ugpcb.com/tag/pcb-via-parasitic-capacitance/) [신호 무결성](https://www.ugpcb.com/tag/signal-integrity/) [via stub](https://www.ugpcb.com/tag/via-stub/) 공유하다:[페이스북](https://www.facebook.com/share.php?u=https%3A%2F%2Fwww.ugpcb.com%2Fnews%2Fpcb-tech%2Fpcb-via-parasitic-capacitance-optimization%2F&title=PCB+Via+Parasitic+Capacitance+Optimization%3A+Three+Physical+Mechanisms+for+Signal+Integrity+-+UGPCB) [지저귀다](https://twitter.com/intent/tweet?via=Twitter&text=PCB+Via+Parasitic+Capacitance+Optimization%3A+Three+Physical+Mechanisms+for+Signal+Integrity+-+UGPCB&url=https%3A%2F%2Fwww.ugpcb.com%2Fnews%2Fpcb-tech%2Fpcb-via-parasitic-capacitance-optimization%2F) [링크드인](https://www.linkedin.com/shareArticle?mini=true&url=https%3A%2F%2Fwww.ugpcb.com%2Fnews%2Fpcb-tech%2Fpcb-via-parasitic-capacitance-optimization%2F&title=PCB+Via+Parasitic+Capacitance+Optimization%3A+Three+Physical+Mechanisms+for+Signal+Integrity+-+UGPCB&source=https://www.ugpcb.com) [왓츠앱](https://api.whatsapp.com/send?text=PCB+Via+Parasitic+Capacitance+Optimization%3A+Three+Physical+Mechanisms+for+Signal+Integrity+-+UGPCB%20-%20https%3A%2F%2Fwww.ugpcb.com%2Fnews%2Fpcb-tech%2Fpcb-via-parasitic-capacitance-optimization%2F) **이전:** [고속 PCB 루프 제어: 복귀 경로 설계가 신호 무결성 및 EMI 성능을 정의하는 방법](https://www.ugpcb.com/news/pcb-tech/electronic-design/high-speed-pcb-loop-control/) ## 관련된 - [고속 PCB 루프 제어: 복귀 경로 설계가 신호 무결성 및 EMI 성능을 정의하는 방법](https://www.ugpcb.com/news/pcb-tech/electronic-design/high-speed-pcb-loop-control/) - [10 PCB 설계 세부 사항이 제품 성공을 결정합니다.: 수석 엔지니어의 핵심 레이아웃 및 라우팅 규칙](https://www.ugpcb.com/news/pcb-tech/pcb-design-details-and-layout-rules/) - [FPC 전체 프로세스 설계 가이드: 디자인-소재-공정 시너지의 핵심 로직을 마스터하세요](https://www.ugpcb.com/news/pcb-tech/fpc-design-and-manufacturing-guide/) - [PCB 설계 세 가지 필수 요소: 레이아웃에 대한 완벽한 가이드, 놓기, 및 라우팅](https://www.ugpcb.com/news/pcb-tech/pcb-design-guidelines/) - [RF PCB 안테나 손실의 세 가지 주요 원인: PCB에서 소모된 3dB 이득을 회수하는 방법 (측정된 데이터로)](https://www.ugpcb.com/news/pcb-tech/rf-pcb-antenna-loss/) - [PCB 구리 타설의 양날의 검: EMI 밸런싱, 수확량, 및 IPC 표준](https://www.ugpcb.com/news/pcb-tech/pcb-copper-pour-2/) - [The “Invisible Killers” Behind Length Matching: 정말로 DDR을 올바르게 라우팅하고 있습니까??](https://www.ugpcb.com/news/pcb-tech/ddr-high-speed-routing/) - [PCB 구리 타설의 이중 특성: 솔리드 대. 부화 구리 - 귀하의 회로에 적합한 것?](https://www.ugpcb.com/news/pcb-tech/pcb-copper-pour/) - [한계를 깨다: NVIDIA Rubin Ultra Orthogonal 백플레인 PCB의 극단적인 기술적 장애물 해독](https://www.ugpcb.com/news/pcb-tech/orthogonal-backplane-pcb/) - [다층 카운트 PCB에 대한 이해: 설계 과제부터 제조 정밀도까지 심층 분석](https://www.ugpcb.com/news/pcb-tech/high-layer-count-pcb-design-and-manufacturing/) ## 답장을 남겨주세요[답장 취소](/news/pcb-tech/pcb-via-parasitic-capacitance-optimization/#respond)