Base Station PCB Assembly
Central Processing Units
Network communication is handled by a Freescale MPC8321 PowerQUICC2 CPU which runs at 200 MHz and has 2x 256 MB Hynix DDR2 RAM. It utilizes a PMC QuadPHY 10 GB controller for the two optical input / saída.
Decoding and encoding of the single bit streams for ADC and DAC are handled by the 3 Altera Cyclone III FPGA and the custom Huawei SD6151RBI controllers.
The single bit streams are treated by the Texas Instrument TMS320 series DSP CPUs:
- TMS320C6410: A fixed-point DSP that only calculates with integer numbers.
- TMS320CT16482: UM 1 GHz DSP CPU that calculates floating point numbers.
Receive Part
The input signal comes in two out of phase lines and is first treated by a Skyworks SKY73021-11 1.7 para 2.2 GHz downconversion mixer to get the frequency from 2.2 GHz to 550 MHz.
- Local Oscillator: An Analog Devices ADF4110B.
- SIPAT SAW Filter: Used for isolation.
- Variable Gain Amplifiers: Analog Devices AD8376, used before the signal lines split out into either a 3G ADC line or 4G ADC line.
3G Line
The analog to digital conversion is handled by the Analog Devices AD6655-10, a 14-bit 150 MSPS chip specifically targeted for 3G base stations.
4G Line
The 4G line has a few more components:
- 2 MCL HSWA+1110 SPDT RF Switch: Feeds into 2 Maxim MAX2039E up/downconversion mixer.
- ADC: Analog Devices AD9230-11-200, a 11-bit 200 MSPS chip.
All timing is handled by the Analog Devices AD9516-3, a 14-output clock generator with a built-in 2 GHz local oscillator.
Transmit Part
The single bit datastream from the Altera Cyclone III FPGA is handled by 2 Analog Devices TxDAC AD9788, specified for 16-bit 800 MSPS.
- Upconversion Modulators: 2 Analog Devices ADL5375-05, with a range from 400 MHz to 6 GHz.
- Ceramic Resonator Band Pass Filter: 5 staged.
- Signal Phase Switching: Transistors and EMC Technology & Florida RF Labs HPJ2F hybrid couplers.
- Pre-Amplifier: Freescale MMG3004NT1 high linearity amplifier, capable of 17 dB amplification in the range of 400 MHz to 2.2 GHz.
Signal Strength Control
To control the signal strength, a MCL 31R5 digital step attenuator sits before the output connector. This is a 31.5 dB attenuator that can work in 0.5 dB steps from a 6-bit serial control interface.
Power Amplifier
The power amplifier uses two stages:
- First Stage: Infineon PTMA180402FL 40 Watt RF LDMOS, feeding two 90 degree out of phase signals to the output stage transistors through a Xinger II XC1900A-03S hybrid coupler.
- Output Stage Transistors: NXP BLF6G20LS-140 140 Watt RF LDMOS.
- Recombination: In a Xinger II XC1900A-03S hybrid coupler before leaving to the diplexer through a circulator.
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