Late-night debugging. A freshly assembled power board powers up—and explodes. MOSFETs shatter. Traces blacken. The project slips further behind schedule.
Too many PCB design engineers know this scene all too well.
When failures occur, engineers often blame component selection or counterfeit parts. But the real culprit usually lies in the PCB design itself—insufficient trace current capacity, inadequate heat dissipation, or unsafe clearance distances. The components simply expose what the design got wrong.
This guide delivers actionable design rules and critical parameters. No fluff. Just standards-based practices that work.
Chapter 1: Trace Current Capacity—Calculate, Don’t Guess
Burned high-current traces rank as the most common failure mode. The root cause is almost always the same: you didn’t calculate the current properly.
A PCB trace’s current-carrying capacity depends on three factors: trace width, copper weight, and allowable temperature rise. IPC-2152, Standard for Determining Current Carrying Capacity in Printed Board Design, is the sole industry standard for determining appropriate internal and external conductor sizes on printed boards as a function of the current carrying capacity required and the acceptable conductor temperature rise.
For external layer copper traces, the simplified formula is:
I = k × W^0.725 × T^0.44
Where: I = current (A), W = trace width (mil), T = copper weight (oz), and k = correction factor—0.048 for external layers, 0.024 for internal layers.
Source: IPC-2152 Standard for Determining Current Carrying Capacity in Printed Board Design (2009)
Prefer a quick reference? Here is the lookup table for external layer 1 oz copper at a 10°C temperature rise:
| Current | Minimum Width | Recommended Width |
|---|---|---|
| 1A | 0.25 mm | 0.3 mm |
| 3A | 0.8 mm | 1.0 mm |
| 5A | 1.5 mm | 2.0 mm |
| 10A | 3.5 mm | 4.0 mm |
| 20A | 8.0 mm | 10.0 mm |
| 30A | 14.0 mm | 16.0 mm |
| 50A | 25.0 mm | 30.0 mm |
Critical reminder: These values apply to external layer traces. Internal layers dissipate heat poorly, so their current capacity drops to roughly 50–60% of external layers.
For copper weight selection: 1 oz suffices below 10A, 2 oz for 10–30A, 3–4 oz for 30–100A. Above 100A, stop routing—use busbars instead.
One nearly cost-free technique: apply solder mask openings on high-current traces, then tinplate the exposed areas. The tin layer increases the effective cross-section and boosts current capacity by 30–50%.
Chapter 2: Thermal Management—Move Heat Out, Fast
Heat is the PCB’s worst enemy—every 10°C rise cuts electrolytic capacitor life in half.
The junction temperature calculation follows the industry-standard thermal resistance network model:
Tj = Ta + P × (Rjc + Rcs + Rsa)
Where: Tj = junction temperature (should not exceed 125°C), P = power dissipation, Rjc = junction-to-case thermal resistance (from the datasheet), and Rsa = heatsink-to-ambient thermal resistance.
Source: JEDEC thermal resistance network model (JESD51 series standards)
How to place thermal vias: This is where many designs fail. FR-4 has a thermal conductivity of just 0.3–0.4 W/m·K, while copper reaches 390 W/m·K—a factor of 1000 difference. Without thermal vias, heat has nowhere to go.
| Parameter | Recommended Value |
|---|---|
| Via diameter | 0.3–0.5 mm |
| Via pitch | 1.0–1.5 mm |
| Via barrel copper | ≥25 μm |
| Coverage | ≥30% of the thermal pad area |
Why keep vias small? Large vias wick solder away during reflow, causing voids and weak joints. A 0.3 mm diameter strikes the best balance.
Chapter 3: Clearance and Creepage—Safety by Design
High-voltage arcing is no joke. According to IEC 60950-1 / IEC 62368-1 (Pollution Degree 2):
| Voltage | Basic Insulation | Reinforced Insulation |
|---|---|---|
| Below 50V | 0.2 mm | 0.4 mm |
| 100V | 0.5 mm | 1.0 mm |
| 250V | 1.5 mm | 3.0 mm |
| 400V | 2.5 mm | 5.0 mm |
| 600V | 3.5 mm | 7.0 mm |
| 1000V | 6.0 mm | 12.0 mm |
Sources: IEC 60950-1 Information technology equipment – Safety; IEC 62368-1 Audio/video, information and communication technology equipment – Safety
Critical distinction: These values represent clearance—the shortest distance through air. Creepage—the shortest path along the insulation surface—can be severely compromised by dust and moisture. Slots (routing a 1 mm+ groove between high and low voltage regions) are far more effective than simply increasing distance.
Chapter 4: Stackup—The Foundation That Decides Everything
Standard 4-layer power board stackup:
- Layer 1: Signal + power traces (top component side)
- Layer 2: Solid ground plane (do not split!)
- Layer 3: Power layer (VCC / VBUS)
- Layer 4: Signal + power traces (bottom side)
Why must Layer 2 be ground? A solid ground plane simultaneously solves three problems: shortest return paths, best shielding, and largest heat-spreading area.
Advanced 6-layer stackup: Signal – Ground – Power 1 – Power 2 – Ground – Signal. Two ground planes sandwiching two power layers deliver optimal EMI performance.
Chapter 5: Layout and Critical Loops
Layout sequence: Power input → Input filtering → Power conversion → Output filtering → Load → Control circuitry (keep it away from the power stage)
Always route the power loop first, then the control signals. Anyone who does it backward will spend their days spinning revisions.
Buck converter critical loops must be minimized—high-frequency switching loop area should stay below 100 mm². Every halving of loop area reduces radiation by approximately 6 dB.
The switch node (SW node) generates the fiercest EMI on the entire board: keep its copper area small, route it far from feedback sense traces, and add an RC snubber when needed (typical values: 10Ω + 1nF).
Current sensing demands a Kelvin (4-wire) connection: two traces carry the current, two traces carry the sense signal. The sense points must originate at the resistor pad roots—never tap off from the high-current path.
Chapter 6: Pre-Production Checklist
Check every item. Skip none:
- All high-current trace capacities calculated per IPC-2152?
- Power loop area minimized?
- Thermal via density ≥30%?
- High-voltage clearances checked against IEC 60950/62368?
- Isolation slots routed?
- Sense resistor uses Kelvin connection?
- Switch node has RC snubber?
- Junction temperature estimated below 125°C?
- Copper temperature rise calculated below 40°C?
- Fabrication shop can handle the copper weight and trace geometries?
Final word: In high-power PCB design, margin is not waste—margin is survival.
For high-power PCB design consultation or PCBA prototyping quotes, please contact our technical team for professional support.
Source Attribution:
- IPC-2152 Standard for Determining Current Carrying Capacity in Printed Board Design (2009), IPC (Association Connecting Electronics Industries)
- IPC-2221C Generic Standard on Printed Board Design (2023), IPC
- IEC 60950-1 Information technology equipment – Safety, International Electrotechnical Commission
- IEC 62368-1 Audio/video, information and communication technology equipment – Safety, International Electrotechnical Commission
- JEDEC thermal resistance network model (JESD51 series), JEDEC Solid State Technology Association
