1. ±5% Is Not a Slogan. It Is a Set of Contract Numbers.
AEC and optical module paddle cards often carry ±10% impedance tolerance in the subtractive spec. By contrast, mSAP specs often state ±5%. That five-point gap means three things on the shop floor. อันดับแรก, the sidewall moves from a trapezoid to a near-rectangle. ที่สอง, etch compensation must follow a board shop formula, not a rule of thumb. Third, shipment must include coupon TDR data from the same panel.
Industry design guidance commonly cites roughly 5–7% manufacturing tolerance for 50 Ω lines. IPC-2141A provides the controlled-impedance design framework. นอกจากนี้, 224G and 112G SerDes discussions often point to ±3% to ±5% impedance precision for mSAP. That range applies to selected layers, not to every layer by default. ดังนั้น, the contract value of mSAP lies in three questions. Which layers use it? What compensation rule drives the artwork? What data proves acceptance?
2. When to Move from Subtractive to mSAP: Judge by Bottlenecks, Not by Frequency Alone
224G and 448G do not force mSAP by themselves. แทน, they raise sensitivity to linewidth deviation and sidewall shape near Nyquist. FineLine and similar field-solver studies rank linewidth, layer spacing, and Dk as major factors. Copper thickness and solder mask rank as minor factors. The sidewall edge angle (W1−W2) is secondary, yet a subtractive trapezoid cannot default to a rectangle in simulation.
In practice, three bottleneck tiers guide the decision.
ชั้น 1: Subtractive still works. L/S stays roughly above 50 ไมโครเมตร. The outline is loose. Differential pair spacing is not crowded. The impedance contract can still accept a ±10% narrative. Conventional subtractive HDI is enough.
ชั้น 2: Subtractive falls short, so key layers use mSAP (ไฮบริด). L/S enters the 25–50 µm band. Differential pair spacing is insufficient under a fixed outline. A near-rectangular section is needed to hold impedance. Eltek process tables list mSAP at 25/25 µm and subtractive at 50/50 ไมโครเมตร. Head:Foot also moves from (1−2/3 CuT):1 for subtractive toward ≈1:1 for mSAP and SAP. At this tier, full-layer buildup is unnecessary. Apply mSAP only to DSP/ASIC breakout and dense differential escape layers. Keep power, พื้น, and sparse signal layers on subtractive processing. This hybrid approach delivers the best cost-performance balance for paddle cards.
ชั้น 3: Full-layer or near-full-layer mSAP. Multiple L/S locations drop below 25 ไมโครเมตร. Microvia stacking, pad escape, and pair spacing crowd together. The contract explicitly requires ±5% and a coupon for every layer. At this stage, ask the ผู้จำหน่าย PCB about capacity and lead time before discussing slogans.
One boundary must remain clear. Unimicron FCBGA roadmaps list Core Layer MSAP at 12/16 ไมโครเมตร. Uyemura UHDI narratives mention 2/2 ไมโครเมตร. Both belong to the สารตั้งต้น IC and package substrate context. They are not default delivery standards for a paddle card. ดังนั้น, the SOW must prohibit citing FCBGA or ABF substrate L/S as module board acceptance criteria.
3. Etch Compensation: Artwork Linewidth Does Not Equal Finished Linewidth
mSAP adds copper only at circuit locations. A flash etch still removes the seed copper. The seed removal step eats spacing and rewrites linewidth.
Glickman gives the governing relationship:
Etch distance = foil thickness (minus cleaning oxidation) + electroless copper thickness + foil tooth + safety margin
Finished minimum space ≈ LDI minimum linewidth + 2 × etch distance
ตัวอย่างเช่น, assume an etch distance of 5.5 µm and an LDI minimum line of 10 µm on the space side. The finished space then reaches about 21 ไมโครเมตร. ในทางกลับกัน, the artwork must draw that space at 10 µm under the compensation rule. Only then does the finished space reach 21 ไมโครเมตร. The product and the coupon on the same panel must share one compensation set. มิฉะนั้น, TDR data will diverge from the physical board.
Seed copper source also belongs in the spec. mSAP usually starts with a base Cu foil and 0.3–1.5 µm electroless copper. SAP typically uses no foil, ยิ่งกว่า 1 µm electroless copper, and a higher adhesion and cost tier. A verbal claim of “full-layer build-up” fails DFM review when it omits the foil-seed versus pure-electroless distinction. บาง, low-roughness foil plus uniform plating and etching keeps etch distance under control.
4. Hybrid Stack-Up: Material Grade Is Not Process Capability
A common misreading treats Megtron 7, ม6, or M8 low-loss material grades as automatic equivalents of mSAP. ในความเป็นจริง, material selection covers Dk, ฟ, and copper foil roughness. Process selection covers linewidth formation. The spec must list them separately.
A hybrid stack-up table should contain at least five columns. Add a note: “Example only; final values require board shop sign-off.”
| ชั้น | กระบวนการ | L/S target | Impedance target | ฟอยล์ / วัสดุ |
|---|---|---|---|---|
| L2 differential escape | mSAP | 25/25 ไมโครเมตร | 90 โอห์ม ± 5% (coupon required) | เอชวีแอลพี + specified Dk/Df grade |
| L3 power | Subtractive | Per current | - | Standard foil |
HVLP foil is no longer optional at 224G and 448G. ที่ 56 กิกะเฮิรตซ์, copper skin depth is about 0.28 ไมโครเมตร. When surface roughness Rz approaches that skin depth, the current path lengthens and conductor loss rises sharply. Based on Hammerstad-Jensen engineering estimates, HVLP with Rz = 4 µm adds roughly +40–60% extra loss at 56 กิกะเฮิรตซ์. HVLP4 with Rz = 1.5 µm adds roughly +10–15%. ที่ 25 กิกะเฮิรตซ์, standard foil with Rz ≈ 10 µm adds about 0.8–1.2 dB/inch more loss than HVLP with Rz ≈ 2 ไมโครเมตร. เพราะเหตุนี้, copper foil roughness is a hard line item in the insertion-loss budget, not a material preference.
5. Cross-Section and TDR: No Coupon Data, No ±5% Claim
Three steps turn ±5% into acceptance.
ขั้นตอน 1: Cross-section checks rectangularity and top/bottom linewidth. Even a near-rectangular mSAP section needs photo-based top and bottom linewidth verification. Do not default to a vertical wall and thereby erase the subtractive trapezoid. คลาส IPC-6012 3 defines microsection acceptance for coupons and sections. A common shop rule keeps the section plane within 10% of the hole diameter. The SOW must state the sampled layers and section criteria. กระบวนการ Aoi linewidth measurement reflects process capability. It cannot replace shipping cross-sections and TDR.
ขั้นตอน 2: TDR follows IPC-TM-650 Method 2.5.5.7. This method is the standard time-domain reflectometry method for พีซีบี ความต้านทานลักษณะ. It calls for a 50 Ω TDR unit with uncertainty ≤ ±0.5 Ω. Common coupon practice calls for at least one coupon per panel, with two preferred. The minimum trace length is 150 มม (6 ใน). The default tolerance is ±10% unless the design file states otherwise. When the contract states ±5%, it must also state layer, reference plane, solder mask condition, TDR rise time, and window. นอกจากนี้, the coupon and the product must share the same panel.
ขั้นตอน 3: Reflow and thermal cycling follow project rules, not slogans. Glickman’s 200 µm pitch work used 10× lead-free reflow plus air/liquid thermal cycling as a reference. MSA does not mandate that level. Many OEMs require 6×, while 10× serves as an engineering safety factor. The SOW should state microvia diameter, stacked-via layers, and whether a 6× or 10× reflow report is required.
6. DFM and Contract Fields: Make ±5% Buyable and Auditable
The following fields fit directly into review minutes and RFQs. They also form the checklist for qualifying an mSAP PCB supplier. Each field should return a signed response.
| สนาม | Required content |
|---|---|
| กระบวนการ | Subtractive / mSAP / SAP; full-layer or layer list |
| Target L/S | ไมโครเมตร; mark “shop capability” หรือ “project target” |
| Artwork compensation | Etch distance or board shop formula; who edits Gerber |
| Seed copper | Foil thickness range + electroless copper thickness range |
| ความต้านทาน | Nominal, ความอดทน, ชั้น, reference plane, solder mask condition, coupon requirement (TDR per IPC-TM-650 2.5.5.7) |
| วัสดุ | Grade + foil type (HVLP/VLP, ฯลฯ); substrate L/S must not replace paddle card criteria |
| ไมโครเวีย | เส้นผ่าศูนย์กลาง, stacked layers, 6×/10× reflow report requirement |
| Lead time and panel | Written quote governs |
| Prohibited item | FCBGA/ABF substrate L/S must not serve as delivery standard |
| Safety standard | อล 796 remains the relevant printed wiring board safety standard; state flammability class in the SOW |
At the inquiry stage, send the stack-up table, impedance table, coupon layers, and acceptance criteria to the board shop for DFM sign-off. This step produces a more executable and auditable quote than a one-line request for “mSAP.” mSAP costs roughly 1.5–2.5× subtractive processing. A hybrid strategy keeps that multiplier on critical layers instead of spreading it across the whole board.
คำชี้แจงแหล่งข้อมูล
- ไอพีซี-2141A, คู่มือการออกแบบสำหรับแผงวงจรอิมพีแดนซ์ควบคุมความเร็วสูง: controlled-impedance design framework; industry practice often cites roughly 5–7% manufacturing tolerance for 50 Ω lines.
- IPC-TM-650 Method 2.5.5.7: standard TDR method for PCB characteristic impedance; 50 Ω TDR unit with uncertainty ≤ ±0.5 Ω.
- คลาส IPC-6012 3: coupon and microsection acceptance requirements; common shop rule keeps the section plane within 10% of hole diameter.
- อล 796: UL safety standard for printed wiring boards; flammability and thermal requirements remain project-specific.
- Glickman and Eltek mSAP process data: etch distance formula, mSAP 25/25 µm example, Head:Foot ≈ 1:1, seed copper 0.3–1.5 µm.
- HVLP copper foil roughness and loss estimates: Rz = 4 µm HVLP adds roughly +40–60% extra loss at 56 กิกะเฮิรตซ์; Rz = 1.5 µm HVLP4 adds roughly +10–15%; ที่ 25 กิกะเฮิรตซ์, standard foil adds about 0.8–1.2 dB/inch more loss than HVLP.
- Industry statements on 224G/448G mSAP impedance precision: roughly ±3% to ±5%; ไฮบริด “critical-layer-only mSAP” is a common industry practice.
- mSAP cost multiplier versus subtractive processing: roughly 1.5–2.5×.
