EMC (전자기 호환성) design is to PCB engineers what battlefield tactics are to military commanders – a single misstep can cost the entire campaign. In today’s era of high-speed digital systems and mixed RF circuits, ~ 위에 85% of radiated emission failures trace back to PCB-level deficiencies in filtering, discontinuous shielding structures, or incorrect grounding strategies. EMC problems are never isolated faults; they are systemic breakdowns.
EMC design ultimately operates on three dimensions: 차폐, filtering, and grounding – shielding traps interference inside a cage, filtering blocks interference on the lines, and grounding gives interference a path to escape. These three elements form a castle’s defense system: shielding is the wall, filtering is the gate, and grounding is the moat. A thick wall is useless if the gate stands open; a sturdy gate is worthless without a moat.
장 1: Shielding – Trapping Interference in a Cage
1.1 The Essence of Shielding
Shielding uses conductive or magnetic materials to form an enclosed surface. This surface confines electromagnetic fields within a defined region or prevents external fields from entering. Shielding addressesspatial coupling – namely capacitive coupling, inductive coupling, and radiative coupling.
When an electromagnetic wave encounters a shield, three phenomena occur:
| Mechanism | 원칙 | Key Influencing Factors |
|---|---|---|
| Reflection loss (아르 자형) | Wave reflection at the shield surface due to impedance mismatch | Material conductivity, wave impedance mismatch |
| Absorption loss (에이) | Wave energy converted to heat during penetration | Material conductivity, permeability, 두께 |
| Multiple reflections (비) | Repeated internal reflections within the shield | Shield thickness, internal structure |
Total shielding effectiveness: SE = R + 에이 + 비 (DB)
Absorption loss A can be calculated asA = 8.69 × (t/δ), where t is shield thickness and δ is skin depth. This meansone skin depth of shielding material provides approximately 9 dB of absorption loss; doubling the thickness adds another 9 DB.
1.2 Electric Field Shielding vs. Magnetic Field Shielding
| Comparison | Electric Field Shielding | Magnetic Field Shielding |
|---|---|---|
| Interference source | 고전압, low current | High current, low voltage |
| 재료 선택 | High conductivity (구리, 알류미늄) | High permeability (철, Mu-metal) |
| 원칙 | Reflects electric field, creates opposing field | Channels magnetic flux, concentrates it inside |
| Grounding requirement | Must be grounded | Not mandatory |
| Thickness requirement | Thin suffices (피부 효과) | Requires sufficient thickness |
1.3 Five Critical Shielding Design Rules
- 재료 선택: Use copper or aluminum for electric fields and far-field; use ferromagnetic materials for low-frequency magnetic fields.
- Seam control: Keep seam lengths below λ/20; use conductive gaskets.
- Aperture control: Keep hole dimensions below λ/20; minimize the number of openings.
- Cable penetration: Use filtered connectors or shielded adapters at penetration points.
- Grounding: The shield must be well grounded; 그렇지 않으면, it becomes an antenna.
Shielding has limitations. Low-frequency magnetic fields are extremely difficult to shield (requiring thick ferromagnetic materials). Apertures and seams severely degrade performance. Shielding is expensive, heavy, and complex to manufacture.Shielding is the last line of defense – prioritize source control and filtering first.
장 2: Filtering – Blocking Interference on the Lines
2.1 The Essence of Filtering
Filtering inserts a frequency-selective network into the signal path. This network passes desired signals while blocking interference. Filtering addressesconducted coupling – interference that propagates through cables.
Low-pass filters are the most common type in EMC applications because most interference is high-frequency while useful power and signals are low-frequency.
2.2 The Power EMI Filter – The Classic EMC Filter
The power EMI filter is standard equipment for switch-mode power supplies. Its typical structure consists of X capacitors, Y capacitors, and common-mode chokes connected between the live, neutral, and ground lines.
| 요소 | Suppression Mode | Typical Parameters |
|---|---|---|
| X capacitor | Differential-mode interference | 0.1–2.2 μF |
| Y capacitor | Common-mode interference | 1–4.7 nF |
| Common-mode choke | Common-mode interference | 1–10 mH |
| Differential-mode inductor | Differential-mode interference | Tens to hundreds of μH |
2.3 The Core Metric: Insertion Loss
Insertion loss (일) is the key parameter for evaluating filter performance. It is defined as the ratio of load-side voltage before and after filter insertion:
IL = 20log₁₀(V₁/V₂) (DB)
당CISPR 17:2011, which specifies methods to measure the radio interference suppression characteristics of passive EMC filtering devices, a quality DC power filter should achievecommon-mode insertion loss ≥ 40 dB and differential-mode insertion loss ≥ 30 DB across the 150 kHz – 30 MHz conducted emission band. CISPR 17 defines test configurations including 50Ω/50Ω symmetrical (differential mode) and asymmetrical (common mode) measurements, as well as non-50Ω systems such as 0.1Ω/100Ω and 100Ω/0.1Ω topologies.
2.4 Four Filter Design Principles
- Common mode first, then differential mode: Common-mode interference is typically harder to handle; prioritize common-mode filter design.
- Place close to the source: Locate the filter as close as possible to the interference source or the sensitive port.
- Mind impedance matching: The filter operates between source impedance and load impedance; impedance mismatch severely degrades performance. Per CISPR 17, asymmetric impedance testing (예를 들어, 0.1Ω/100Ω) should be used to verify filter performance under worst-case conditions.
- Ground well: The common terminal of Y capacitors and the filter must connect to ground with low impedance.
장 3: Grounding – Giving Interference a Path to Escape
3.1 The Essence of Grounding
Grounding serves two core purposes: safety grounding (protecting personnel by providing a fault current path) 그리고signal grounding (providing a reference potential for circuits and a low-impedance return path for interference currents). EMC focuses primarily on signal grounding.
Grounding addresses theloop problem – interference currents need a low-impedance return path. Poor grounding forces interference currents through unintended paths, creating coupling.
3.2 Ground Impedance – Inductance Dominates at High Frequencies
The impedance of a PCB trace or wire includes resistance R and inductive reactance XL:
Z = R + jXL = R + j2πfL
Consider a PCB trace 10 cm long, 1.5 mm wide, 그리고 50 μm 두께:
- 저항: R = ρL/s = 0.02 × 0.1 / (1.5 × 0.05) ≈ 0.026 오
- Inductance: 약0.08 μH (0.8 μH/m self-inductance)
- ~에 1 MHz, 유도성 리액턴스: XL = 2π × 1×10⁶ × 0.08×10⁻⁶ ≈ 0.5 오 -19 times the resistance!
Key conclusion: 고주파에서, inductance dominates impedance.Shortening the ground path is the most effective way to reduce impedance. A solid ground plane offers the lowest impedance. Flat conductors (구리박) have lower high-frequency impedance than round conductors (철사).
3.3 Three Grounding Methods
| Grounding Method | 원칙 | 주파수 범위 | Advantage | Disadvantage |
|---|---|---|---|---|
| Single-point grounding | All ground points connect to one point | <1 MHz | No ground loops | High impedance at high frequencies |
| Multi-point grounding | Each ground point connects locally to ground plane | >10 MHz | Low high-frequency impedance | Ground loops possible |
| Hybrid grounding | Single-point at low frequencies, multi-point at high frequencies | Broadband | Balances low and high frequencies | Complex design |
In practice, most products contain both low-frequency and high-frequency circuits.Hybrid grounding is the mainstream engineering approach – single-point grounding for low-frequency sections (avoiding ground loops) and multi-point grounding for high-frequency sections (reducing impedance). Capacitors and inductors enable “frequency-selective grounding.”
3.4 The Solid Ground Plane Advantage
A solid ground plane provides a low-impedance return path for current, reduces noise, and improves circuit reliability. On multilayer boards, dedicating large areas of the PCB to ground and connecting components along the shortest possible routes minimizes ground impedance. A continuous ground plane acts as a shield underneath high-speed or sensitive traces, absorbs stray electromagnetic fields, 누화 감소, and improves EMC performance.
장 4: Three-Way Synergy – 1+1+1 > 3
4.1 Why Synergy Is Essential
Each technique – shielding, filtering, and grounding – has limitations when used alone. But when they work together, the effect multiplies:
| 대본 | 결과 |
|---|---|
| Shield not grounded | Nearly useless; the shield becomes a secondary radiator |
| Filter not grounded | High-frequency filtering fails |
| Poor grounding system | Shield becomes antenna; filter becomes coupling path |
| All three working together | Maximum effectiveness |
4.2 사례 연구: Switch-Mode Power Supply EMC Design
단계 1 – Source control: Optimize MOSFET gate drive (reduce switching slew rate). Optimize PCB 레이아웃 (minimize power loop area). Add RCD snubber circuits.Reducing the power loop area by 50% can lower radiated emissions by approximately 12 DB.
단계 2 – Filter design: Install X capacitors, common-mode chokes, and Y capacitors at the input (power EMI filter). Add an LC filter at the output. Place decoupling capacitors at the control IC power pins.
단계 3 – Grounding design: Separate power ground from signal ground; connect them at a single point. Ground Y capacitors locally to the chassis. Ground the heatsink.
단계 4 – Shielding design: Add shielding cans over MOSFETs and rectifiers. Add a Faraday shield layer to the transformer. Route critical signals on inner layers with ground planes on both sides.
4.3 사례 연구: High-Speed Digital Board EMC Design
단계 1 – Source control: Control signal rise times (series termination resistors). Keep clock traces away from I/O connectors. Route differential pairs symmetrically.
단계 2 – Grounding design: Maintain a solid ground plane; avoid splits. Dedicate a separate ground plane section for the I/O area and connect it to the chassis.
단계 3 – Filter design: Add common-mode chokes on I/O lines. Use π-type filters at the power entry point. Place decoupling capacitors at every IC power pin.In a standard six-layer board stack-up, solid ground planes on layers 2 그리고 5 provide 15–25 dB of radiation suppression across the 30 MHz - 1 GHz 대역.
단계 4 – Shielding design: Use shielded I/O connectors. Apply conductive gaskets at chassis seams. Route critical signals on inner layers.
장 5: Design Priority – Source Control Always Comes First
5.1 The Five-Layer Defense
| 층 | Measure | 효과 | 비용 |
|---|---|---|---|
| 층 1 | Source control (component selection, layout optimization) | Fundamental solution | 가장 낮습니다 |
| 층 2 | Loop design (minimize loop area, 임피던스 매칭) | Significant improvement | 낮은 |
| 층 3 | 필터링 | Effective suppression | 중간 |
| 층 4 | Grounding | Systematic improvement | 중간 |
| 층 5 | Shielding | Last-resort solution | 제일 높은 |
Core principle: Solve at the source whenever possible; filter only what you cannot eliminate at the source; shield only as a last resort.
5.2 Why Source Control Matters Most
| Comparison | 소스 제어 | Remedial Measures (Filtering/Shielding) |
|---|---|---|
| 효과 | 근본적인 | Symptom treatment |
| 비용 | Nearly zero | Requires additional components/materials |
| 신뢰할 수 있음 | 높은 | May degrade with temperature/aging |
| 디자인 자유 | 높은 | Constrained by space and cost |
| Production consistency | 좋은 | Affected by component tolerances |
Reducing MOSFET switching speed by 30% can lower high-frequency noise by 6–10 dB – more effective than any filter.
장 6: EMC Design Checklist – Quick Reference
Schematic Stage
- □ Power input has an EMI filter; every IC power pin has a decoupling capacitor
- □ High-speed signals have termination resistors
- □ I/O lines have TVS/ESD protection
- □ Clocks have RC filtering or spread spectrum
- □ Isolation between high-voltage and low-voltage sections meets IPC-2221 requirements
PCB Layout Stage
- □ Power loop area minimized; power devices placed close together
- □ Analog/digital/power/RF sections partitioned
- □ I/O connectors grouped together and placed away from noise sources
- □ Clock traces kept away from I/O; routed on inner layers with ground planes on both sides
- □Ground plane kept solid; avoid splits
Mechanical/Structural Stage
- □ Shielding cans added over critical noise sources; shield grounding resistance ≤ 0.1 오
- □ Seams treated with conductive gaskets; gap length < λ/20
- □ Shielded cables and connectors used
- □ Shield, PCB ground, and chassis ground connected with low impedance
- □ Ventilation holes kept below λ/20; use waveguide vents when necessary
결론: EMC Design Is Systems Engineering
EMC design is not about point solutions – it is aboutsystems engineering.
Shielding, filtering, and grounding form an inseparable trio.
But remember the core principle: source control comes first, filtering provides midfield support, shielding is the last line of defense, and grounding is the foundation that runs through everything.
When you face those dancing emission spikes on the spectrum analyzer in the EMC lab, trace them back to the decisions made on your PCB 설계 drawings – every choice about placement, 라우팅, decoupling, 접지, and shielding – those are the choices that truly determine success or failure.
EMC is not measured into a product; it is designed into it.
Data Source Statement:
The technical data and standards cited in this article are based on the following sources:
- The shielding effectiveness formula SE = R + 에이 + B and the absorption loss formula A = 8.69 × (t/δ) are referenced from electromagnetic shielding theory literature.
- The insertion loss definition IL = 20log₁₀(V₁/V₂) and the CISPR 17:2011 standard requirements (common-mode ≥40 dB, differential-mode ≥30 dB across the 150 kHz–30 MHz band) are referenced from CISPR 17:2011 -Methods of measurement of the suppression characteristics of passive EMC filtering devices.
- PCB trace impedance calculations R = ρL/s and inductive reactance XL = 2πfL are referenced from PCB grounding and interference suppression technical literature.
- PCB-level EMC data (85% of radiated emission failures trace to PCB-level issues; six-layer board ground plane suppression of 15–25 dB) are referenced from EMC troubleshooting and practical design literature.
- The IPC-2221 standard framework for PCB electrical requirements (접지, 차폐, 신호 무결성) is referenced from IPC-2221 –인쇄 기판 설계에 대한 일반 표준.
- UL PCB safety standards (UL 796 for rigid printed wiring boards) are referenced from UL 796 -Standard for Printed-Wiring Boards.
