A PCB quotation often leaves only a few percentage points for price negotiation. Jedoch, one design parameter can move the cost of the same board by 10% Zu 25%. This gap shows a simple truth. The real lever sits in design, not in last-minute bargaining.
Design for Cost (DFC) turns cost into an engineering variable. The goal is clear. Use standard processes for standard boards. Pay a “precision premium” only where signal integrity and reliability truly need it. The sections below cover eight decision points in order of cost impact. Each data point cites IPC, UL, or a traceable source.
Erste, Understand the Cost Structure
Raw materials dominate PCB cost, and the copper-clad laminate (CCL) is usually the largest single material item. CCL cost itself depends on copper foil, Harz, and glass fabric. daher, an over-specified laminate choice amplifies cost through the entire CCL-to-PCB chain.
| Laminattyp | Relative Cost | Tg Range | Dk / Df | Typical Use |
|---|---|---|---|---|
| Standard FR-4 | 1.0× (Grundlinie) | 130–140°C | 4.2–4,5 / 0.02 | Unterhaltungselektronik |
| Mid-Tg FR-4 | 1.15–1.25× | 170–180°C | 4.0–4.2 / 0.015 | Industrial and communication |
| Hoch-Tg FR-4 | 1.25–1.40× | 180–210°C | 3.8–4.0 / 0.012 | Automotive and servers |
| Hochgeschwindigkeitslaminat | 2.0–4.0× | - | 3.0–3.8 / 0.004 | RF and high-speed differential |
Decision rules. Erste, use halogenated laminate when the product has no halogen-free mandate; it costs about 10% Zu 20% weniger. Zweite, use mid-Tg laminate when the product has no high-Tg requirement; it costs about 10% Zu 20% weniger. Dritte, use standard Dk laminate when impedance and loss budgets allow it; it costs about 30% Zu 40% less than Low-Dk laminate. Zusätzlich, the source material ranks four CCL suppliers in ascending price order at roughly 1 : 1.03 : 1.17 : 1.32. For products at or below 10 layers and 3-stage HDI, teams should evaluate the lower-cost suppliers first. For higher layer counts and advanced HDI, teams should consider the higher-end suppliers.
FR-4 base material usually needs a UL 94 V-0 Flammenbewertung. This rating is a baseline requirement, not a premium feature. daher, teams should not treat it as a cost differentiator.
Zweite, Copper Thickness Has Two Cost Steps
Surface copper thickness and via copper thickness are highly sensitive cost variables. Copper itself costs money. Thick copper also adds plating time and etching difficulty. Darüber hinaus, thicker copper worsens undercut during etching. Infolge, minimum line width and spacing must open up. Ansonsten, open and short defects will erase any cost saving.
For via copper, IPC-6012 gives clear anchors. Klasse 2 requires average via copper of at least 20 µm and a minimum of at least 18 µm. Klasse 3 requires average via copper of at least 25 µm and a minimum of at least 20 µm. Consumer electronics and standard industrial control products can use Class 2. Automotive and medical products may require Class 3. In that case, 25 µm via copper is a compliance cost, not a soft target.
High aspect ratios make uniform plating harder. daher, designers should control board thickness and hole size together. They should not rely on extra plating to fix a poor aspect ratio. This approach protects yield and controls PCB manufacturing cost.
Dritte, Hole Size and Hole Count Drive Drilling Cost
Laser via size has little cost impact, because the HDI flow already prices it as a package. Mechanical hole size creates the real cost gap.
Smaller holes wear drill bits faster. They also reduce stack height during drilling. Folglich, drilling efficiency falls and cost rises. Using finished hole size as the dimension, relative cost is about as follows: ≥0.30 mm is the baseline; 0.25 mm adds about 5% Zu 10%; 0.20 mm adds about 10% Zu 20%; 0.15 mm adds about 20% Zu 35%. daher, the preferred design order is 0.30 mm, Dann 0.25 mm, Dann 0.20 mm, Dann 0.15 mm. Designers should avoid mechanical holes below 0.20 mm unless BGA fan-out or routing density truly requires them.
Hole count is another linear cost driver. More laser holes and mechanical holes mean more drilling time and more drill bit wear. Teams can merge ground and power via arrays. They can replace redundant vias with copper pours. They can also reserve multi-via per net only for critical nets. Special holes such as half-holes and PTH holes larger than 6.0 mm also trigger extra charges. Designers should evaluate these features early in layout.
Vierte, Line Width and Spacing: 5/5 mil Is the Practical Default
The cost curve is almost flat between 6/6 mil und 5/5 Mil. A 6/6 mil rule (0.15 mm / 0.15 mm) uses a standard process and adds no premium. A 5/5 mil rule (0.127 mm / 0.127 mm) is a standard HDI process at most board houses. Its price is almost the same as 6/6 Mil. Zusammen, these two tiers can cover more than 80% of signal lines on a typical board.
The real cost jump starts at 4/4 Mil. This tier enters fine-line processing and adds about 15% Zu 25% to cost. Bei 3.5 mil und unten, cost rises by 30% Zu 50%, and yield drops clearly. Designers should use this tier only for 0.5 mm pitch BGA fan-out or impedance lines with no alternative.
IPC-2221B provides a current-carrying framework that prevents unnecessary fine lines. Die Formel lautet I = k × ΔT^0,44 × A^0,725. Hier, k is 0.048 for external layers and 0.024 für Innenschichten. A is the cross-sectional area in mil², and ΔT is the allowed temperature rise. Power and ground nets can use wide traces or copper pours above 6 Mil. daher, designers can reserve 5/5 mil for signals and limit 4/4 mil to true high-density areas.
IPC-2221B also sets minimum spacing for 0–15 V. Internal layers need 2 Mil (0.05 mm). External layers without coating need 4 Mil (0.1 mm). Infolge, low-voltage digital areas do not need extreme spacing rules.
Fifth, Via Filling and Surface Finish: Separate Need from Habit
Via filling has a clear cost ladder: ink plug < Harzstopfen < Vippo (via-in-pad plated over). Ink plug costs about 30% Zu 50% less than resin plug. Resin plug costs about 30% Zu 40% less than VIPPO. These options also have different engineering meanings. Ink plug simply blocks the hole. Resin plug fills the hole and provides mechanical support. VIPPO fills the hole and rebuilds a flat pad for via-in-pad assembly. daher, VIPPO is necessary only when via-in-pad assembly truly needs a flat pad. A standard via with solder mask plug or resin plug can meet most reliability needs.
Surface finish follows a similar cost order: OSP < leaded HASL < bleifreies HASL < gold plating or immersion gold. OSP has the lowest material cost. Jedoch, sample shops may quote OSP higher than HASL, because OSP boards are harder to panel with other orders. In volume production, OSP usually shows its cost advantage.
ENIG costs mainly come from the gold layer. IPC-4552B gives a typical ENIG window of nickel 3.0–6.0 µm and gold 0.05–0.10 µm. The source material also notes that each 0.025 µm increase in gold thickness adds about 3% Zu 5% to cost. daher, teams should use selective surface finish. They can keep ENIG on BGA pads, goldene Finger, and key contacts. They can use OSP on shield frames, large copper openings, and non-soldering test points. This approach cuts gold area without hurting assembly yield.
Sixth, Board Thickness and Panelization: The Underused Structural Levers
Board thickness from 1.2 mm zu 1.6 mm shows little price difference. Once thickness reaches 2.0 mm or more, lamination and drilling costs start to rise. More layers with a thinner board also increase process difficulty. Zum Beispiel, a 10-layer 1.0 mm board usually costs less than a 10-layer 0.8 mm board. The thinner board demands tighter lamination tolerance and warpage control. daher, designers should not default to 1.6 mm. When the mechanical structure allows, 1.2 mm or 1.0 mm can cut material use without hurting reliability.
Panelization is a pure design lever. The utilization formula is Utilization = Single-board area × Panel count ÷ Large-panel area × 100%. A panel length-to-width ratio of 1.2 Zu 1.5 gives high substrate utilization. A panel size above 200 mm usually lowers utilization. For spacing, 1.6 mm zu 2.0 mm balances routing strength and router-bit wear. For outline design, straight lines and right angles are best. Teams should use V-Cut before routing, and standard routing before laser cutting. Routed slots below 1.0 mm add process time and raise tool breakage risk. Main boards often use 2 Zu 6 hoch, mit 4 up as a good default. Small boards often use 8 Zu 20 hoch, mit 12 up as a good default. Rotation and mirroring can raise utilization from below 70% to above 85% for irregular boards.
Seventh, Anchor Cost Reduction in Standards
These eight decision points lead to one conclusion. Effective PCB cost reduction does not come from finding a cheaper PCB supplier alone. It comes from replacing “high-spec habit” with the graded logic of IPC standards. IPC-6012 Klasse 2 und Klasse 3 define different via copper levels. IPC-2221B provides current and spacing tables. IPC-4552B sets an ENIG thickness window. Zusammen, these standards help teams allocate reliability where it matters.
For PCBA cost control, teams should start with a design self-check before they request a PCB quote or PCBA quotation. They should state laminate grade, via copper class, surface-finish areas, and panel size in the request. A capable PCB supplier can then quote with clear cost drivers. Zusamenfassend, design discipline is the largest cost lever. It needs no negotiation with the board house. It only needs a careful review of every default value before the design freeze.
Erklärung zur Datenquelle
- IPC-6012 (qualification and performance specification for rigid printed boards): Klasse 2 average via copper ≥20 µm and minimum ≥18 µm; Klasse 3 average ≥25 µm and minimum ≥20 µm.
- IPC-2221B (generic standard on printed board design): current formula I = k × ΔT^0.44 × A^0.725, with k = 0.048 for external layers and k = 0.024 für Innenschichten; minimum spacing for 0–15 V is 2 Mil (0.05 mm) on internal layers and 4 Mil (0.1 mm) on external layers without coating.
- IPC-4552B (ENIG-Spezifikation): typical nickel window 3.0–6.0 µm and gold window 0.05–0.10 µm; source material notes each 0.025 µm gold increase adds about 3% Zu 5% kosten.
- UL 94 V-0: common flame rating for FR-4 base material.
- Panel utilization formula: Utilization = Single-board area × Panel count ÷ Large-panel area × 100%.
- Source material cost ratios: halogenated versus halogen-free laminate saves about 10% Zu 20%; mid-Tg versus high-Tg saves about 10% Zu 20%; standard Dk versus Low-Dk saves about 30% Zu 40%; CCL supplier price ratio about 1 : 1.03 : 1.17 : 1.32.
- Source material hole-cost ratio: ≥0.30 mm baseline; 0.25 mm +5% Zu 10%; 0.20 mm +10% Zu 20%; 0.15 mm +20% Zu 35%.
- Source material line-width cost: 4/4 Mil +15% Zu 25%; ≤3.5 mil +30% Zu 50%.
- Source material via-fill cost: ink plug 30% Zu 50% lower than resin plug; Harzstopfen 30% Zu 40% lower than VIPPO.
