Einführung: A Question Most Engineers Never Ask
In der Welt von Hochgeschwindigkeits-PCB-Design, Impedanzkontrolle is a topic that everyone talks about, yet few truly master. Every layout engineer knows that an unexpected impedance discontinuity in a signal path is bad news. We all want our Hochgeschwindigkeitsplatine links to maintain a steady, constant impedance from start to finish — 50 ohms for single-ended or 100 ohms differential for differential traces.
But reality is never that simple. A complete high-speed signal path includes not just traces but also vias, Anschlüsse, Kabel, AC coupling capacitors, BGA solder balls, and other structures. Each of these introduces a potential impedance discontinuity. Einerseits, we invest significant effort in optimization. Auf der anderen Seite, we must accept that discontinuities will inevitably affect high-speed link performance to some degree.
Yet there is one question that most engineers have never seriously considered:
If your link must have an impedance low point, and you could choose where to place it — where would you put it?
Close to the transmitter? Close to the receiver? Right in the middle? Does it even make a difference?
Heute, we will answer this question with simulation data from a 25Gbps link.
1. The Physical Nature of Impedance Discontinuity
Before diving into the simulation, we need to understand why impedance discontinuity degrades signal quality.
The characteristic impedance of a transmission line is determined by its inductance and capacitance per unit length:
WoL is inductance per unit length andC is capacitance per unit length. When a signal encounters an impedance change along the transmission line, a portion of the signal energy reflects back to the source. The reflection coefficient is given by:
WoZL is the load impedance andZ0 ist die charakteristische Impedanz. WannZL ≠Z0, Γ ≠ 0, and reflection occurs.
For microstrip structures, the characteristic impedance follows the IPC-2141 standard:
Where ε*r* is the dielectric constant of the board material, H is the dielectric thickness, UndW ist die Spurbreite. Any change in trace width, reference plane discontinuity, or variation in dielectric constant directly alters the instantaneous impedance.
According to IPC-2251, a design enters the “hohe Geschwindigkeit” domain when the signal rise time is short enough that the transmission line must be treated as a distributed parameter element rather than a lumped element. IPC-2251 further states that when trace length exceeds the critical length — typically one-tenth of the signal’s propagation distance during the rise time — controlled impedance design becomes mandatory. At 25Gbps, signal rise times typically range from 20 Zu 30 picoseconds, and the critical length is only about 3 Zu 5 Millimeter. This means nearly every trace requires careful impedance management.
IPC-2141 specifies that impedance deviation across high-speed PCB channels should be kept within 5%, with critical channels requiring 3% oder besser. Jedoch, IPC-2141A also acknowledges that completely eliminating impedance discontinuities in real-world designs is impractical — vias, Anschlüsse, and pads inherently introduce parasitic capacitance and inductance.
2. Simulation Setup: A 5-Inch 25Gbps Link
To answer the question of where to place an impedance low point, we built a 5-inch (etwa 127 mm) high-speed transmission link running at 25Gbps.
Baseline Case: We first established an ideal link with no impedance discontinuity — the entire link was a perfect 100-ohm differential transmission line. We assigned active models to the transmitter and receiver chips. The transmitter sent a 25Gbps PRBS (pseudo-random binary sequence) pattern through the 5-inch link to the receiver.
The simulation result: The baseline eye diagram showed an eye height of 360 mV. Keep this number in mind — it serves as our “perfect score” reference for all subsequent comparisons.
Test Cases: We then introduced a fixed impedance low point into the link (simulating the impedance drop caused by a via or connector). We placed this low point at four different positions: 1 Zoll, 2 Zoll, 3 Zoll, Und 4 inches from the transmitter. All other link parameters remained identical.
3. Simulation Results: The Position Difference Is Stunning
The simulation results for the four positions are summarized below:
| Impedance Low Point Position | Receiver Eye Height |
|---|---|
| No low point (Grundlinie) | 360 mV |
| 1 inch from transmitter | 186 mV |
| 2 inches from transmitter | 249 mV |
| 3 inches from transmitter | 271 mV |
| 4 inches from transmitter | 298 mV |
Data Interpretation:
- 1-inch position: Eye height dropped from 360 mV to 186 mV — a48.3% Reduktion. The signal lost nearly half its margin.
- 2-inch position: Eye height recovered to 249 mV — a33.9% Verbesserung over the 1-inch case.
- 3-inch position: Eye height reached 271 mV — a45.7% Verbesserung over the 1-inch case.
- 4-inch position: Eye height reached 298 mV — a60.2% Verbesserung over the 1-inch case, Und1.6 mal the eye height of the worst-case placement.
The same impedance low point, placed at different positions along the link, produced drastically different eye diagram results. This outcome likely exceeds the intuition of most engineers.
4. Why Does This Happen? The Physical Mechanisms
Why does the same impedance discontinuity cause such different effects when placed close to the transmitter versus close to the receiver? Several physical mechanisms are at work:
1. Multiple Reflection Superposition
When a signal encounters an impedance low point, a portion of its energy reflects back toward the transmitter. This reflected wave travels back, reflects again at the transmitter, and then propagates forward to superpose with subsequent signal symbols. If the impedance low point is close to the transmitter, the round-trip delay is short, and the reflected wave quickly overlaps with the following data bits, causing severe intersymbol interference (ISI). According to IPC-2251 signal integrity guidelines, return loss should be kept below -20 dB to minimize reflection impact.
2. Signal Attenuation Accumulation
As a signal propagates along a transmission line, it suffers from both conductor loss (Hauteffekt) and dielectric loss. The skin depth is given by:
Where ω is angular frequency, μ ist die Permeabilität, and σ is conductivity. At gigahertz frequencies, the skin depth is only a few micrometers, and conductor loss increases dramatically. The longer the signal travels before reaching the impedance discontinuity, the more energy it has already lost— and the less energy remains to reflect back and cause interference.
This is why an impedance low point placed farther from the transmitter (after more signal attenuation has occurred) has a smaller impact on the eye diagram.The discontinuity itself hasn’t changed; the signal arriving at it simply has less “Stärke” links.
3. Rise Time and Temporal Overlap of Reflections
The shorter the signal rise time, the more likely reflected waves will overlap with the main signal in the time domain. At 25Gbps, the unit interval (Ui) ist nur 40 picoseconds. Any reflection delay can cause interference within the same or adjacent symbols. When the impedance low point is close to the transmitter, reflected waves return quickly and overlap more severely with subsequent symbols.
5. Design Implications: Where Should You Place Impedance Discontinuities?
Based on the simulation results and physical analysis above, we can derive the following design guidelines:
Prinzip 1: If you cannot eliminate a discontinuity, place it as close to the receiver as possible.
The simulation data clearly shows that moving an impedance discontinuity from near the transmitter to near the receiver in a 25Gbps link can improve eye height from 186 mV to 298 mV— a performance gap of 60% for the same impedance low point, purely based on placement.
Prinzip 2: Prioritize impedance continuity near the transmitter.
The area near the transmitter is where the signal has the most energy. Any impedance discontinuity here causes reflections with the greatest destructive potential. daher, components that may introduce impedance discontinuities — such as BGA pads, Durchkontaktierungen, and AC coupling capacitors — should be placed as far from the transmitter as possible. Alternativ, apply back-drilling to vias near the transmitter and optimize anti-pad dimensions.
Prinzip 3: Use simulation to guide placement.
Different data rates and different link lengths may yield different optimal positions for impedance discontinuities. Während der Designphase, use SI simulation tools such as HyperLynx to perform parameter sweeps and quantitatively evaluate the eye margin for different placement options. Let data guide your decisions.
Prinzip 4: Pay attention to the entire link’s impedance profile.
IPC-2141 emphasizes that impedance control is not just about meeting a target value — it is about maintaining instantaneous impedance continuity along the entire signal path. Use TDR (time-domain reflectometry) to perform impedance profiling of your Leiterplatte and identify all discontinuity locations and their magnitudes. Follow IPC-TM-650 2.5.5.7a for characteristic impedance testing procedures.
6. Abschluss
Impedance discontinuities are an unavoidable reality in high-speed PCB design. But as our simulation experiment has shown: the same impedance low point, placed at different positions along the link, can have effects ranging from “catastrophic” Zu “akzeptabel” — and the difference between those outcomes can determine whether a 25Gbps project succeeds on the first spin or requires three board revisions.
The next time you must place a via, a connector, or a capacitor in a high-speed PCB layout, take an extra five minutes to ask yourself: Is this impedance discontinuity really in the right place?
Natürlich, the ideal scenario is alwaysno impedance discontinuity at all. But in the real world, Wann “perfection” is unattainable, “choosing the right position” is the best possible solution.
For PCB impedance control, Simulation der Signalintegrität, and high-speed PCB design and manufacturing services, please contact our technical team for a free design review (Kostenlose DFM-Rezension) and impedance control quote. We provide one-stop Leiterplatte solutions from simulation to mass production.
Data Sources:
- IPC-2141ADesign Guide for High-Speed Controlled Impedance Circuit Boards, IPC – Association Connecting Electronics Industries
- IPC-2251Designleitfaden für die Verpackung elektronischer Hochgeschwindigkeitsschaltungen, IPC – Association Connecting Electronics Industries
- IPC-TM-650 2.5.5.7aCharacteristic Impedance Test Methods, IPC – Association Connecting Electronics Industries
- Simulation data in this article is based on a 25Gbps active link simulation model using PRBS pattern, 5-inch FR-4 transmission line, 100-ohm differential impedance.
